The need for lower resistance and capacitance in interconnect dielectric films caused by the ever-increasing miniaturization of semiconductor devices has led to the use of copper to form interconnects and vias rather than aluminum. When those structures are formed from copper a dual damascene process is typically used, in view of the difficulty in dry etching copper.
As the line width of interconnects continues to decrease, additional measures must be taken to guarantee the reliability of damascene interconnects that include trenches and vias. Brain et. Al., “Low-k Interconnect Stack with a Novel Self-Aligned Via Patterning Process for 32 nm High Volume Manufacturing,” IITC2009, session 13.1 (pp. 249-251), discloses a hardmask process for making the tightest pitch layers in the interconnect stack, to enable production of Self-Aligned Vias (SAV). In this and other conventional dual damascene processes, the vias are first created in the ILD, followed by the trenches, and then the vias and trenches are lined with a metallic Cu barrier and then filled with bulk Cu, followed by planarization.
U.S. Pat. No. 7,067,919 discloses a damascene interconnect method in which a metal mask having a trench pattern is formed on an oxide film overlying an interconnect film. The via pattern is defined in a layer of photo resist overlying the metal mask, and the interconnect film is etched to form the vias. After via formation, the photo resist film is removed and the trenches are formed using the metal mask, followed by filling the trenches and vias with copper.
U.S. Pat. No. 7,524,752 discloses removing a metal mask after forming trenches and vias, filling the trenches and vias with metal, followed by chemical mechanical processing (CMP). Dimensional variation that could occur if the metal mask were removed by CMP after filling the trenches and vias is said to be reduced.
The present inventor has however found that these techniques have various problems. Low-k film is typically used for the interconnect dielectric layers, so as to reduce unwanted interlayer capacitance. On the other hand, a metal mask is used to form an opening such as a via or through hole or trench, in order for the feature to be self-aligned. However, when using metal mask to form fine patterns, there is a difference in the stresses between the low-k film and the metal mask, which causes strain at the interfaces between these layers, and which makes it difficult to obtain a desired pattern with a high degree of precision.